| Editorial Review | "Reinders and Jeffers have written an outstanding book about much more than the Intel (R) Xeon Phi (TM). This is a comprehensive overview of the challenges in realizing the performance potential of advanced architectures, including modern multi-core processors and many-core coprocessors. The authors provide a cogent explanation of the reasons why applications often fall short of theoretical performance, and include steps that application developers can take to bridge the gap. This will be recommended reading for all of my staff." -James A. Ang, Ph.D. Senior Manager, Extreme-scale Computing, Sandia National Laboratories "The authors' consummate knowledge of the architecture shines through in this excellent introduction to the fundamentals of programming for the Intel (R) Xeon Phi (TM) coprocessor." I highly recommend this engaging treatise to programmers interested in effectively utilizing the Intel (R) Xeon Phi (TM) coprocessor." -R. Glenn Brook, Ph.D., Chief Technology Officer, Joint Institute for Computational Sciences, Director, Application Acceleration Center of Excellence, University of Tennessee / Oak Ridge National Laboratory "The authors have provided a very readable, big-picture introduction to programming the Intel Xeon Phi Coprocessor. By chronicling step-by-step optimizations of several computational kernels, software interfaces are illustrated for getting the most out of key architectural features of the Intel Xeon Phi Coprocessor." -James L. Schwarzmeier, Cray Inc, January 2013." "This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come." -Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword |
| About the Author | Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel (R) MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012. |
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