System-On-Chip Test Architectures: Nanometer Design For Testability Hardcover English by Laung-Terng Wang - 24-Jan-08
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| Publisher | ELSEVIER SCIENCE & TECHNOLOGY |
| ISBN 13 | 9780123739735 |
| Author | Laung-Terng Wang, Charles E. Stroud, Nur Touba |
| Language | English |
| Book Subtitle | Nanometer Design For Testability |
| Book Description | Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. , , This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. |
| About the Author | Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007). |
| Publication Date | 24-Jan-08 |
| Number of Pages | 896 |
System-On-Chip Test Architectures: Nanometer Design For Testability Hardcover English by Laung-Terng Wang - 24-Jan-08
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